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A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors

Abstract

This paper introduces a novel low-complexity multiple-input multiple-output (MIMO) detector tailored for single-carrier frequency division-multiple access (SC-FDMA) systems, suitable for efficient hardware implementations. The proposed detector starts with an initial estimate of the transmitted signal based on a minimum mean square error (MMSE) detector. Subsequently, it recognizes less reliable symbols for which more candidates in the constellation are browsed to improve the initial estimate. An efficient high-throughput VLSI architecture is also introduced achieving a superior performance compared to the conventional MMSE detectors with less than 28% added complexity. The performance of the proposed design is close to the existing maximum likelihood post-detection processing (ML-PDP) scheme, while resulting in a significantly lower complexity, i.e., 4.5×102 and 7×104 times fewer Euclidean distance (ED) calculations in the 16-QAM and 64-QAM schemes, respectively. The proposed design for the 16-QAM scheme is fabricated in a 0.13 μm CMOS technology and fully tested, achieving a 1.332 Gbps throughput, reporting the first fabricated design for SC-FDMA MIMO detectors to-date. A soft version of the proposed architecture is also introduced, which is customized for coded systems.

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications pdf

 

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A High-Throughput VLSI Architecture for Hard and Soft SC-FDMA MIMO Detectors,minimum mean square error,maximum likelihood post-detection processing ,Soft SC-FDMA MIMO Detectors,,VLSI Implementation of Reconfigurable Low Power Fir Filter Architecture,High Performance Reconfigurable FIR Filter Architecture Using Optimized Multiplier,constant shift method,VLSI Project,VLSI projects,verilog projects,FPGA implementaion,VHDL projectss

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