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Network-on-Chip for Turbo Decoders

Abstract

The multi-application specific instruction processor (ASIP) architecture is a promising candidate for flexible high-throughput turbo decoders. This brief proposes a network-on-chip (NoC) structure for multi-ASIP turbo decoders. The process of turbo decoding is studied, and the addressing patterns for turbo codes in long term evolution (LTE) and High Speed Downlink Packet Access (HSDPA) are analyzed. Based on this analysis, two techniques, subnetworking and calculation sequence, are proposed for reducing the complexity of the NoC. The implementation results show that the proposed structure gives an improvement of 53% for HSDPA and 133% for LTE in throughput/area efficiency compared with state-of-the-art NoC solutions. .

Network-on-Chip for Turbo Decoders pdf

 

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Network-on-Chip for Turbo Decoders,Turbo decoder,Network on chip,High Speed Downlink Packet Access,turbo codes in long term evolution,Network-on-Chip verilog code,Turbo Decoder verilog code,Network-on-Chip VHDL code,Network on chip VHDL codes

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