We Offers Network on Chip Verilog code and NOC Verilog Code, NOC Router Verilog Code

Advanced fabrication technologies and scaling have made it possible to integrate a large number of processor cores onto a single die, allowing us to obtain an entire Network-on-Chip (NoC). An example of a NoC with DRAM memory controllers and Dual Inline Memory Modules are shown in Fig 1, where a system consisting of 16 cores is shown. Arriving data is stored at the input buffers, which are divided into Virtual Channels (VC) to prevent deadlockand increase throughput. The VC allocator selects one VC for each input, and the switch allocator decides where each input will be routed to at the output port.

Network on Chip is a new paradigm to make the interconnections inside a System on Chip (SoC). Bus structures is used to make interconnections in SoC. New technology will not be satisfied by bus structure, as integration surges it becomes narrow and in the worst case it begins to block traffic. NoC is a technology that is intended to solve the short coming of buses. Network in NoC technology replaces the bus structure. Blocks communicate with each other and sends data in the form of packet over this network. NoC network consists of routers, route the data packets and wires connect devices to routers and routers to other routers. Processors, memories and other IPblocks (Intellectual Property) or processing elements (PE) are connected to routers. The router which is a main component should be properly designed to implement efficient NoC architecture. In this paper we designed and simulated the 1X4 tree topology NoC Router using Verilog HDL and implemented on Spartan3 Xc3s400 FPGA.